The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
The dynamic random access memory (DRAM) industry has been trying to resolve issues related to high-performance DRAM that is used in high-end application processors such as smartphone or tablet processors. Today the industry is using low-power (LP) double-data-rate (DDR) DRAM such as LP-DDR2 and DDR3 DRAM. Throughout the present disclosure, the term DDR or DDRx, where x is an integer greater than or equal to 1, will be used to denote DDR DRAM or DDRx DRAM, respectively. The abbreviation DRAM will be omitted to improve readability.
The Joint Electron Devices Engineering Council (JEDEC) is presently discussing LP-DDR3 and DDR4 as well as ultra-wide I/O DRAM. Ultra-wide I/O DRAM is supposed to address bandwidth challenge but at the expense of requiring expensive through-silicon via (TSV) technology. In addition to the cost, for each generation of ultra-wide I/O DRAM, the customers would need to redesign the TSV and/or the system-on-chip (SOC) utilizing the ultra-wide I/O DRAM.